1. Field of the Invention
The present invention relates to a solid-state imaging device and an imaging apparatus in which pixels each having a photoelectric conversion element are arranged in a matrix shape. Further, the present invention relates to a signal reading method of reading signals from the pixels.
This application claims the benefits of Japanese Patent Application No. 2011-264941, filed Dec. 2, 2011, the disclosure of which is hereby incorporated herein by references in its entirety.
2. Description of the Related Art
An imaging apparatus such as a digital still camera that converts light to an electrical signal and outputs an image signal uses a solid-state imaging device as an image generation unit that generates an image. In recent years, as the number of pixels and the frame rate has increased in the field of solid-state imaging devices, there is a need for technology to realize high-speed reading. Further, there is a need for technology to achieve low power consumption.
As a type of solid-state imaging device, there is a CMOS (including MOS)-type image sensor (hereinafter described as a “CMOS image sensor”) that can be manufactured through the same process used to manufacture a CMOS integrated circuit. The CMOS image sensor has a configuration in which, for each pixel, charges are converted into an electrical signal and the electrical signals read from the pixels are processed in parallel in each pixel column. Through the parallel processing in each pixel column, the reading speed for pixel signals can be improved.
In recent years, a demand for high-speed imaging is increasing. In an image sensor, this demand is satisfied by reducing the number of readings (the number of rows/the number of lines) in a vertical direction. One example of a method of reducing the number of readings in the vertical direction includes a method called interlaced scanning in which pixels are skipped in a certain row period.
Further, when a method disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-263526 is used, the number of readings in the vertical direction can be reduced more than in normal interlaced scanning. As a result, pixel signals can be read at a high speed. In a CMOS image sensor shown in Japanese Unexamined Patent Application, First Publication No. 2010-263526, a plurality of systems of driving signal lines for simultaneously driving a plurality of pixels in a row direction are provided in one row. Alternatively, in a CMOS image sensor shown in Japanese Unexamined Patent Application, First Publication No. 2010-263526, a plurality of systems of vertical signal lines that transfer pixel signals output from the pixels in a vertical direction are provided in one column. In order to input a pixel signal to a column processing unit provided in each column, the CMOS image sensor selects one of a plurality of rows for each column and outputs a pixel signal from the selected row. Accordingly, column processing of pixel signals of a plurality of rows can be performed through column processing once.
For example, a case in which pixel signals are read from only pixels 400 and 401 among pixels constituting a Bayer array illustrated in FIG. 21 is considered. In FIG. 21, Gr and Gb indicate green pixels. Rr indicates a red pixel. Bb indicates a blue pixel. The color of each pixel corresponds to a color of a color filter arranged on each pixel.
When reading of the pixel signals is performed, first, the pixels 400 in first and second rows are selected. The pixel signals output from the pixels 400 are then input to a column processing unit of each column. After the pixel signals output from the pixels 400 are processed by the column processing unit, pixels 401 of fifth and sixth rows are selected. The pixel signals output from the pixels 401 are then input to the column processing unit of each column. The pixel signals output from the pixels 401 are processed by the column processing unit. Accordingly, the pixel signals of the two rows are simultaneously read per four rows. Since column processing of a plurality of rows of pixel signals is performed through one column process, the pixel signals can be read at a high speed.
In the solid-state imaging device disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-263526, a configuration in which a plurality of systems of driving signal lines are provided in one row has been adopted. The solid-state imaging device is configured to select only the pixels 400 among pixels of the first and second rows and read pixel signals, as illustrated in FIG. 21. Further, the solid-state imaging device is configured to select only the pixels 401 among pixels of the fifth and sixth rows and read pixel signals, as illustrated in FIG. 21. Alternatively, in the solid-state imaging device disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-263526, a configuration in which a plurality of systems of vertical signal lines are provided in one column has been adopted.